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@ -2,21 +2,22 @@
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Rust pretty blatantly just inherits C11's memory model for atomics. This is not
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due this model being particularly excellent or easy to understand. Indeed, this
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model is quite complex and known to have [several flaws][C11-busted]. Rather,
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it is a pragmatic concession to the fact that *everyone* is pretty bad at modeling
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model is quite complex and known to have [several flaws][C11-busted]. Rather, it
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is a pragmatic concession to the fact that *everyone* is pretty bad at modeling
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atomics. At very least, we can benefit from existing tooling and research around
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C.
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Trying to fully explain the model in this book is fairly hopeless. It's defined
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in terms of madness-inducing causality graphs that require a full book to properly
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understand in a practical way. If you want all the nitty-gritty details, you
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should check out [C's specification (Section 7.17)][C11-model]. Still, we'll try
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to cover the basics and some of the problems Rust developers face.
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in terms of madness-inducing causality graphs that require a full book to
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properly understand in a practical way. If you want all the nitty-gritty
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details, you should check out [C's specification (Section 7.17)][C11-model].
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Still, we'll try to cover the basics and some of the problems Rust developers
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face.
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The C11 memory model is fundamentally about trying to bridge the gap between
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the semantics we want, the optimizations compilers want, and the inconsistent
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chaos our hardware wants. *We* would like to just write programs and have them
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do exactly what we said but, you know, *fast*. Wouldn't that be great?
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The C11 memory model is fundamentally about trying to bridge the gap between the
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semantics we want, the optimizations compilers want, and the inconsistent chaos
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our hardware wants. *We* would like to just write programs and have them do
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exactly what we said but, you know, *fast*. Wouldn't that be great?
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@ -41,13 +42,14 @@ x = 2;
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y = 3;
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```
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This has inverted the order of events *and* completely eliminated one event. From
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a single-threaded perspective this is completely unobservable: after all the
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statements have executed we are in exactly the same state. But if our program is
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multi-threaded, we may have been relying on `x` to *actually* be assigned to 1 before
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`y` was assigned. We would *really* like the compiler to be able to make these kinds
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of optimizations, because they can seriously improve performance. On the other hand,
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we'd really like to be able to depend on our program *doing the thing we said*.
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This has inverted the order of events *and* completely eliminated one event.
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From a single-threaded perspective this is completely unobservable: after all
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the statements have executed we are in exactly the same state. But if our
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program is multi-threaded, we may have been relying on `x` to *actually* be
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assigned to 1 before `y` was assigned. We would *really* like the compiler to be
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able to make these kinds of optimizations, because they can seriously improve
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performance. On the other hand, we'd really like to be able to depend on our
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program *doing the thing we said*.
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@ -55,19 +57,20 @@ we'd really like to be able to depend on our program *doing the thing we said*.
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# Hardware Reordering
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On the other hand, even if the compiler totally understood what we wanted and
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respected our wishes, our *hardware* might instead get us in trouble. Trouble comes
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from CPUs in the form of memory hierarchies. There is indeed a global shared memory
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space somewhere in your hardware, but from the perspective of each CPU core it is
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*so very far away* and *so very slow*. Each CPU would rather work with its local
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cache of the data and only go through all the *anguish* of talking to shared
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memory *only* when it doesn't actually have that memory in cache.
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respected our wishes, our *hardware* might instead get us in trouble. Trouble
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comes from CPUs in the form of memory hierarchies. There is indeed a global
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shared memory space somewhere in your hardware, but from the perspective of each
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CPU core it is *so very far away* and *so very slow*. Each CPU would rather work
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with its local cache of the data and only go through all the *anguish* of
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talking to shared memory *only* when it doesn't actually have that memory in
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cache.
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After all, that's the whole *point* of the cache, right? If every read from the
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cache had to run back to shared memory to double check that it hadn't changed,
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what would the point be? The end result is that the hardware doesn't guarantee
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that events that occur in the same order on *one* thread, occur in the same order
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on *another* thread. To guarantee this, we must issue special instructions to
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the CPU telling it to be a bit less smart.
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that events that occur in the same order on *one* thread, occur in the same
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order on *another* thread. To guarantee this, we must issue special instructions
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to the CPU telling it to be a bit less smart.
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For instance, say we convince the compiler to emit this logic:
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@ -82,27 +85,27 @@ x = 1; y *= 2;
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Ideally this program has 2 possible final states:
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* `y = 3`: (thread 2 did the check before thread 1 completed)
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* `y = 6`: (thread 2 did the check after thread 1 completed)
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* `y = 3`: (thread 2 did the check before thread 1 completed) y = 6`: (thread 2
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* `did the check after thread 1 completed)
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However there's a third potential state that the hardware enables:
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* `y = 2`: (thread 2 saw `x = 2`, but not `y = 3`, and then overwrote `y = 3`)
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It's worth noting that different kinds of CPU provide different guarantees. It
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is common to seperate hardware into two categories: strongly-ordered and weakly-
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ordered. Most notably x86/64 provides strong ordering guarantees, while ARM and
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provides weak ordering guarantees. This has two consequences for
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concurrent programming:
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is common to separate hardware into two categories: strongly-ordered and weakly-
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ordered. Most notably x86/64 provides strong ordering guarantees, while ARM
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provides weak ordering guarantees. This has two consequences for concurrent
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programming:
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* Asking for stronger guarantees on strongly-ordered hardware may be cheap or
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even *free* because they already provide strong guarantees unconditionally.
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Weaker guarantees may only yield performance wins on weakly-ordered hardware.
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* Asking for guarantees that are *too* weak on strongly-ordered hardware
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is more likely to *happen* to work, even though your program is strictly
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incorrect. If possible, concurrent algorithms should be tested on
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weakly-ordered hardware.
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* Asking for guarantees that are *too* weak on strongly-ordered hardware is
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more likely to *happen* to work, even though your program is strictly
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incorrect. If possible, concurrent algorithms should be tested on weakly-
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ordered hardware.
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@ -110,58 +113,54 @@ concurrent programming:
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# Data Accesses
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The C11 memory model attempts to bridge the gap by allowing us to talk about
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the *causality* of our program. Generally, this is by establishing a
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*happens before* relationships between parts of the program and the threads
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that are running them. This gives the hardware and compiler room to optimize the
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program more aggressively where a strict happens-before relationship isn't
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established, but forces them to be more careful where one *is* established.
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The way we communicate these relationships are through *data accesses* and
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*atomic accesses*.
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The C11 memory model attempts to bridge the gap by allowing us to talk about the
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*causality* of our program. Generally, this is by establishing a *happens
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before* relationships between parts of the program and the threads that are
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running them. This gives the hardware and compiler room to optimize the program
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more aggressively where a strict happens-before relationship isn't established,
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but forces them to be more careful where one *is* established. The way we
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communicate these relationships are through *data accesses* and *atomic
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accesses*.
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Data accesses are the bread-and-butter of the programming world. They are
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fundamentally unsynchronized and compilers are free to aggressively optimize
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them. In particular, data accesses are free to be reordered by the compiler
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on the assumption that the program is single-threaded. The hardware is also free
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to propagate the changes made in data accesses to other threads
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as lazily and inconsistently as it wants. Mostly critically, data accesses are
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how data races happen. Data accesses are very friendly to the hardware and
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compiler, but as we've seen they offer *awful* semantics to try to
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write synchronized code with. Actually, that's too weak. *It is literally
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impossible to write correct synchronized code using only data accesses*.
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them. In particular, data accesses are free to be reordered by the compiler on
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the assumption that the program is single-threaded. The hardware is also free to
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propagate the changes made in data accesses to other threads as lazily and
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inconsistently as it wants. Mostly critically, data accesses are how data races
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happen. Data accesses are very friendly to the hardware and compiler, but as
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we've seen they offer *awful* semantics to try to write synchronized code with.
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Actually, that's too weak. *It is literally impossible to write correct
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synchronized code using only data accesses*.
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Atomic accesses are how we tell the hardware and compiler that our program is
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multi-threaded. Each atomic access can be marked with
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an *ordering* that specifies what kind of relationship it establishes with
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other accesses. In practice, this boils down to telling the compiler and hardware
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certain things they *can't* do. For the compiler, this largely revolves
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around re-ordering of instructions. For the hardware, this largely revolves
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around how writes are propagated to other threads. The set of orderings Rust
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exposes are:
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* Sequentially Consistent (SeqCst)
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* Release
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* Acquire
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* Relaxed
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multi-threaded. Each atomic access can be marked with an *ordering* that
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specifies what kind of relationship it establishes with other accesses. In
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practice, this boils down to telling the compiler and hardware certain things
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they *can't* do. For the compiler, this largely revolves around re-ordering of
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instructions. For the hardware, this largely revolves around how writes are
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propagated to other threads. The set of orderings Rust exposes are:
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* Sequentially Consistent (SeqCst) Release Acquire Relaxed
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(Note: We explicitly do not expose the C11 *consume* ordering)
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TODO: negative reasoning vs positive reasoning?
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TODO: "can't forget to synchronize"
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TODO: negative reasoning vs positive reasoning? TODO: "can't forget to
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synchronize"
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# Sequentially Consistent
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Sequentially Consistent is the most powerful of all, implying the restrictions
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of all other orderings. Intuitively, a sequentially consistent operation *cannot*
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be reordered: all accesses on one thread that happen before and after it *stay*
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before and after it. A data-race-free program that uses only sequentially consistent
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atomics and data accesses has the very nice property that there is a single global
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execution of the program's instructions that all threads agree on. This execution
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is also particularly nice to reason about: it's just an interleaving of each thread's
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individual executions. This *does not* hold if you start using the weaker atomic
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orderings.
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of all other orderings. Intuitively, a sequentially consistent operation
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*cannot* be reordered: all accesses on one thread that happen before and after a
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SeqCst access *stay* before and after it. A data-race-free program that uses
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only sequentially consistent atomics and data accesses has the very nice
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property that there is a single global execution of the program's instructions
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that all threads agree on. This execution is also particularly nice to reason
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about: it's just an interleaving of each thread's individual executions. This
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*does not* hold if you start using the weaker atomic orderings.
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The relative developer-friendliness of sequential consistency doesn't come for
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free. Even on strongly-ordered platforms sequential consistency involves
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@ -173,26 +172,26 @@ confident about the other memory orders. Having your program run a bit slower
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than it needs to is certainly better than it running incorrectly! It's also
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*mechanically* trivial to downgrade atomic operations to have a weaker
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consistency later on. Just change `SeqCst` to e.g. `Relaxed` and you're done! Of
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course, proving that this transformation is *correct* is whole other matter.
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course, proving that this transformation is *correct* is a whole other matter.
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# Acquire-Release
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Acquire and Release are largely intended to be paired. Their names hint at
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their use case: they're perfectly suited for acquiring and releasing locks,
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and ensuring that critical sections don't overlap.
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Acquire and Release are largely intended to be paired. Their names hint at their
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use case: they're perfectly suited for acquiring and releasing locks, and
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ensuring that critical sections don't overlap.
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Intuitively, an acquire access ensures that every access after it *stays* after
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it. However operations that occur before an acquire are free to be reordered to
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occur after it. Similarly, a release access ensures that every access before it
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*stays* before it. However operations that occur after a release are free to
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be reordered to occur before it.
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*stays* before it. However operations that occur after a release are free to be
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reordered to occur before it.
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When thread A releases a location in memory and then thread B subsequently
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acquires *the same* location in memory, causality is established. Every write
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that happened *before* A's release will be observed by B *after* it's release.
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that happened *before* A's release will be observed by B *after* its release.
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However no causality is established with any other threads. Similarly, no
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causality is established if A and B access *different* locations in memory.
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