From bdb189862ac74e531d8fc32e1e7de4270ce46ff1 Mon Sep 17 00:00:00 2001 From: Jared Flatow Date: Fri, 4 Dec 2020 22:23:03 -0800 Subject: [PATCH] Update atomics.md --- src/atomics.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/atomics.md b/src/atomics.md index f0590b3..05ab207 100644 --- a/src/atomics.md +++ b/src/atomics.md @@ -71,7 +71,7 @@ cache. After all, that's the whole point of the cache, right? If every read from the cache had to run back to shared memory to double check that it hadn't changed, what would the point be? The end result is that the hardware doesn't guarantee -that events that occur in the same order on *one* thread, occur in the same +that events that occur in some order on *one* thread, occur in the same order on *another* thread. To guarantee this, we must issue special instructions to the CPU telling it to be a bit less smart.