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@ -89,7 +89,7 @@ In the previous example, we used the fact that `&mut u32` can't be aliased to pr
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that writes to `*output` can't possibly affect `*input`. This let us cache `*input`
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that writes to `*output` can't possibly affect `*input`. This let us cache `*input`
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in a register, eliminating a read.
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in a register, eliminating a read.
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By caching this read, we knew that the the write in the `> 10` branch couldn't
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By caching this read, we knew that the write in the `> 10` branch couldn't
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affect whether we take the `> 5` branch, allowing us to also eliminate a
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affect whether we take the `> 5` branch, allowing us to also eliminate a
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read-modify-write (doubling `*output`) when `*input > 10`.
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read-modify-write (doubling `*output`) when `*input > 10`.
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