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Remove illegal space.

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Sorry, I'm the useless-details sheriff.
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WarmongeringBeaver 4 years ago committed by Alexis Beingessner
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commit 8413980b07
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@ -96,8 +96,8 @@ However there's a third potential state that the hardware enables:
* `y = 2`: (thread 2 saw `x = 1`, but not `y = 3`, and then overwrote `y = 3`) * `y = 2`: (thread 2 saw `x = 1`, but not `y = 3`, and then overwrote `y = 3`)
It's worth noting that different kinds of CPU provide different guarantees. It It's worth noting that different kinds of CPU provide different guarantees. It
is common to separate hardware into two categories: strongly-ordered and weakly- is common to separate hardware into two categories: strongly-ordered and weakly-ordered.
ordered. Most notably x86/64 provides strong ordering guarantees, while ARM Most notably x86/64 provides strong ordering guarantees, while ARM
provides weak ordering guarantees. This has two consequences for concurrent provides weak ordering guarantees. This has two consequences for concurrent
programming: programming:

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